As is well known in the art, tracking loops are generally used to vary RC filter parameters which in the integrated circuit manufacturing process may vary as much as 35 percent from their nominal value. The tracking loop works to track this variation which can occur due to manufacture or temperature variation. This enables filter corner parameters to be easily adjusted to maintain some predetermined tolerance. More specifically, typical tracking loop circuits use a method of time-constant measurement that is not entirely immune from the effects of input offsets, comparator delay and/or component parasitics. The effect of these parasitics results in an error in the RC time-constant measurement, which in turn results in bandwidth error in any filter or other tuned circuit which the loop is intended to optimize.
Presently, prior art tracking loops use no offset or delay independent topology, which can be problematic in terms of the effect of circuit parasitics on the accuracy of the tracking loop. An example of a tracking loop design of this type is disclosed in IEEE 1997 Custom Integrated Circuits Conference publication entitled “A 3V gm C-Filter with On-Chip Tuning for CDMA,” at pages 5.6.1–5.6.4.
Thus, the need exists for an optimal tracking loop topology that can take into account a very precise time reference, generated on-chip, using an accurate crystal oscillator. Preferably, the tracking loop should be able to tune either a resistor or capacitor in the filter or RC combination to obtain the desired nominal frequency response of the filter. The tuning loop can then be used to tune the response of any type of continuous-time filter.